1. Field
This disclosure generally relates to electronic design automation. More specifically, this invention relates to a technique for adjusting cumulative delay values in graph-based static timing analysis.
2. Related Art
Rapid advances in computing technology have made it possible to perform trillions of computational operations each second on data sets that are sometimes as large as trillions of bytes. These advances can be largely attributed to the exponential increase in the size and complexity of integrated circuits.
Because of this increase in size and complexity of integrated circuits, it has become necessary to use sophisticated tools to verify timing constraints in circuit designs, such as static timing analysis (STA). During graph-based STA, worst-case delay values are accumulated along nodes in a graph-based representation of a circuit by considering the delay values associated with different edges incident on these nodes without enumerating all possible paths through the circuit. Using this graph-based STA, one or more critical paths in the circuit can be identified. Then, path-based STA is performed to determine the slack values more accurately by reducing pessimism in the identified paths.
Note that on-chip variations in timing-related parameters during the design and fabrication of integrated circuits are often modeled in STA techniques using derating factors, which are used to change (or derate) delay values to reflect on-chip variation. Because STA can perform a reasonably accurate timing analysis for many large integrated circuits within a reasonable amount of time, it has emerged as the method of choice for verifying timing constraints for large integrated circuits.
Large integrated circuits often include multiple power supplies that define separate power domains. Intentional differences and unintentional variations in the supply voltages provided by these power supplies directly impact the delay values in these integrated circuits.
Unfortunately, existing approaches for performing STA in multiple-power-domain circuits are either inaccurate, or inefficient, or both. In some techniques, a graph-based STA, which is designed to work on single-power-domain circuits, is performed to identify a set of paths, and a more detailed path-based STA is performed on the identified paths to account for the multiple power-domains. Unfortunately, since the graph-based STA that is used in these approaches does not take into account the multiple power-domains in the circuit, these techniques are fundamentally inaccurate. This is because the identified paths on which the path-based STA is performed may not include the worst-case path, and hence, this technique may completely miss the worst-case path.
In other techniques, an exhaustive approach is used to consider all possible voltage combinations. If there are V discrete voltages per domain in N power domains, the number of STA runs equals VN. Thus, in a circuit with 7 power domains that each has a minimum and a maximum supply voltage, the number of STA runs is 27 or 128. Since the number of STA runs required in this approach grows exponentially with the number of power domains, this approach is simply impractical for circuits with a large number of power domains.